HD6432621 Hitachi, HD6432621 Datasheet - Page 667
HD6432621
Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
1.HD6432621.pdf
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19.4
The registers used to control the on-chip flash memory when enabled are shown in table 19-3.
In order to access these registers, the FLSHE bit in SCRX must be set to 1 (except for RAMER,
SCRX).
Table 19-3 Register Configuration
Register Name
Flash memory control register 1
Flash memory control register 2
Erase block register 1
Erase block register 2
RAM emulation register
Flash memory power control register*
Serial control register X
Notes: *1 Lower 16 bits of the address.
19.5
19.5.1
FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode
or erase-verify mode for addresses H'00000 to H'3FFFF is entered by setting SWE1 bit to 1 when
FWE = 1, then setting the PV1 or EV1 bit. Program mode for addresses H'00000 to H'3FFFF is
entered by setting SWE1 bit to 1 when FWE = 1, then setting the PSU1 bit, and finally setting the
P1 bit. Erase mode for addresses H'00000 to H'3FFFF is entered by setting SWE1 bit to 1 when
FWE = 1, then setting the ESU1 bit, and finally setting the E1 bit. FLMCR1 is initialized by a
reset, and in hardware standby mode and software standby mode. Its initial value is H'80 when a
high level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash
memory is disabled, a read will return H'00, and writes are invalid.
*2 To access these registers, set the FLSHE bit to 1 in serial control register X. Even if
*3 When a high level is input to the FWE pin, the initial value is H'80.
*4 When a low level is input to the FWE pin, or if a high level is input and the SWE1 bit in
*5 FLMCR1, FLMCR2, EBR1, EBR2, RAMER, and FLPWCR are 8-bit registers.
*6 An invalid register in the H8S/2623.
Register Configuration
Register Descriptions
Flash Memory Control Register 1 (FLMCR1)
FLSHE is set to 1, if the chip is in a mode in which the on-chip flash memory is
disabled, a read will return H'00 and writes are invalid. Writes are also invalid when the
FWE bit in FLMCR1 is not set to 1.
FLMCR1 is not set, these registers are initialized to H'00.
Use byte access on these registers.
6
Abbreviation
FLMCR1 *
FLMCR2 *
EBR1 *
EBR2 *
RAMER *
FLPWCR *
SCRX
5
5
5
5
5
5
R/W
R/W *
R *
R/W *
R/W *
R/W
R/W *
R/W
2
2
2
2
2
Initial Value
H'00 *
H'00
H'00 *
H'00 *
H'00
H'00 *
H'00
3
4
4
4
Address *
H'FFA8
H'FFA9
H'FFAA
H'FFAB
H'FEDB
H'FFAC
H'FDB4
1
623
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