HD6432621 Hitachi, HD6432621 Datasheet - Page 222

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

7.9.3
Even if a bus request is received from a bus master with a higher priority than that of the bus
master that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. There are specific times at which each bus master can relinquish the bus.
CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC,
the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of
the bus is as follows:
DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated.
The DTC can release the bus after a vector read, a register information read (3 states), a single data
transfer, or a register information write (3 states). It does not release the bus during a register
information read (3 states), a single data transfer, or a register information write (3 states).
7.10
In a reset, the H8S/2626 Series or H8S/2623 Series, including the bus controller, enters the reset
state at that point, and an executing bus cycle is discontinued.
178
The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
discrete operations, as in the case of a longword-size access, the bus is not transferred between
the operations. See Appendix A.5, Bus States During Instruction Execution, for timings at
which the bus is not transferred.
If the CPU is in sleep mode, it transfers the bus immediately.
Bus Transfer Timing
Resets and the Bus Controller