HD6432621 Hitachi, HD6432621 Datasheet - Page 538

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HD6432621

Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 13.2.7, Serial
Status Register (SSR).
However, the setting conditions for the TEND bit, are as shown below.
Bit 2
TEND
0
1
Note: etu: Elementary Time Unit (time for transfer of 1 bit)
494
Description
Transmission is in progress
[Clearing conditions]
Transmission has ended
[Setting conditions]
When 0 is written to TDRE after reading TDRE = 1
When the DTC is activated by a TXI interrupt and write data to TDR
Upon reset, and in standby mode or module stop mode
When the TE bit in SCR is 0 and the ERS bit is also 0
When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a
1-byte serial character when GM = 0 and BLK = 0
When TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after transmission of a
1-byte serial character when GM = 0 and BLK = 1
When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a
1-byte serial character when GM = 1 and BLK = 0
When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a
1-byte serial character when GM = 1 and BLK = 1
(Initial value)

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