HD6432621 Hitachi, HD6432621 Datasheet - Page 1026

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

TCSR1—Timer Control/Status Register 1*
Notes: TCSR is write-protected by a password to prevent accidental overwriting. For details see section 12.2.5, Notes on Register Access.
982
Bit
Initial value
Read/Write
* 1 Only 0 can be written to these bits (to clear these flags).
* 2 This register is not available, and must not be accessed, in the H8S/2623 Series.
R/(W)
Overflow flag
0
1
OVF
7
0
[Clearing]
(1) When 0 is written to TME bit;
(2) When 0 is written to OVF bit after reading TCSR when OVF=1.
[Setting]
When TCNT overflows (H'FF
When internal reset request generation is selected in watchdog timer mode,
OVF is cleared automatically by the internal reset.
*1
Timer mode select
0
1
WT/IT
Interval timer mode: Interval timer interrupt (WOVI) request sent to CPU
when overflow occurs at TCNT
Watchdog timer mode: Reset or NMI interrupt request sent to CPU when
overflow occurs at TCNT
R/W
6
0
Timer enable
0
1
Initializes TCNT to H’00 and disables the counting operation
TCNT performs counting operation
TME
R/W
Prescaler select
0
1
5
0
H'00).
TCNT counts the divided clock output by the ø-based prescaler
TCNT counts the divided clock output by the øSUB-based prescaler (PSS)
Reset or NMI
2
0
1
PSS
R/W
NMI interrupt request
Internal reset request
4
0
Clock select 2 to 0
Note: *The overflow cycle starts when TCNT starts counting from
PSS CKS2 CKS1 CKS0
0
1
H'FFA2
RST/NMI
H'00 and ends when an overflow occurs.
R/W
0
1
0
1
3
0
0
1
0
1
0
1
0
1
CKS2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R/W
2
0
ø/2
ø/64
ø/128
ø/512
ø/2048
ø/8192
ø/32768
ø/131072
øSUB/2
øSUB/4
øSUB/8
øSUB/16
øSUB/32
øSUB/64
øSUB/128
øSUB/256
Clock
CKS1
R/W
1
0
(when øSUB = 32.768 kHz)
(when ø = 20 MHz)
Overflow cycle*
25.6 s
819.2 s
1.6 ms
6.6 ms
26.2 ms
104.9 ms
419.4 ms
1.68 s
15.6 ms
31.3 ms
62.5 ms
125 ms
250 ms
500 ms
1 s
2 s
CKS0
R/W
0
0
WDT1