HD6432621 Hitachi, HD6432621 Datasheet - Page 982

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HD6432621

Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
TCR1—Timer Control Register 1
938
Bit
Initial value
Read/Write
:
:
:
7
0
CCLR1
R/W
Counter clear
Note: * Synchronous operation setting is performed by setting the
6
0
0
1
Note: This setting is invalid when channel 1 is in phase counting
Input clock edge select
0
1
0
1 TCNT cleared by counter clearing for another channel
0
1
TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
performing synchronous clearing/synchronous operation *
CCLR0
SYNC bit in TSYR to 1.
0
1
R/W
5
0
mode, and also when ø/1 or overflow/underflow of
another channel is selected as the input clock.
Count at rising edge
Count at falling edge
Count at both edges
Note: This setting is invalid when channel 1 is in phase
Time prescaler
0
1
CKEG1
0
1
0
1
R/W
counting mode.
4
0
0
1
0
1
0
1
0
1
Internal clock: counts on ø/1
Internal clock: counts on ø/4
Internal clock: counts on ø/16
Internal clock: counts on ø/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
Internal clock: counts on ø/256
Counts on TCNT2 overflow/underflow
H'FF20
CKEG0
R/W
3
0
TPSC2
R/W
2
0
TPSC1
R/W
1
0
TPSC0
R/W
0
0
TPU1

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