HD6432621 Hitachi, HD6432621 Datasheet - Page 690

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HD6432621

Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
646
Notes: *1 Preprogramming (setting erase block data to all "0") is not necessary.
*2 Verify data is read in 16-bit (W) units.
*3 Set only one bit in EBR1 and 2. More than 2 bits cannot be set.
*4 Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn.
Increment
address
NG
NG
Figure 19-12 Erase/Erase-Verify Flowchart
Set block start address to verify address
H'FF dummy write to verify address
Clear ESU1 bit in FLMCR1
*4
Clear SWE1 bit in FLMCR1
Set SWE1 bit in FLMCR1
Set ESU1 bit in FLMCR1
Clear EV1 bit in FLMCR1
Clear E1 bit in FLMCR1
Set EV1 bit in FLMCR1
Set E1 bit in FLMCR1
Last address of block?
tcswe: Wait ( 1) s
Verify data = all "1"?
erasing of all erase
tsswe: Wait (x) s
tcesu: Wait ( ) s
tsesu: Wait (y) s
tsevr: Wait ( ) s
Set EBR1 and 2
tcev: Wait ( ) s
tsev: Wait ( ) s
tse: Wait (z) ms
Read verify data
tce: Wait ( ) s
End of erasing
Enable WDT
Disable WDT
blocks?
End of
n = 1
Start
OK
OK
OK
*1
NG
*3
Start erase
Halt erase
*2
Clear SWE1 bit in FLMCR1
Clear EV1 bit in FLMCR1
tcswe: Wait ( 1) s
tcev: Wait ( ) s
Erase failure
n
(N)?
OK
NG
n
n + 1

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