HD6432621 Hitachi, HD6432621 Datasheet - Page 472

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI)
request and receive error interrupt (ERI) request generation when serial receive data is transferred
from RSR to RDR and the RDRF flag in SSR is set to 1.
Bit 6
RIE
0
1
Note:* RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF
Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI.
Bit 5
TE
0
1
Notes: *1 The TDRE flag in SSR is fixed at 1.
Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI.
Bit 4
RE
0
1
Notes: *1 Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which
428
flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0.
*2 In this state, serial transmission is started when transmit data is written to TDR and the
*2 Serial reception is started in this state when a start bit is detected in asynchronous
TDRE flag in SSR is cleared to 0.
SMR setting must be performed to decide the transfer format before setting the TE bit
to 1.
retain their states.
mode or serial clock input is detected in clocked synchronous mode.
SMR setting must be performed to decide the transfer format before setting the RE bit
to 1.
Description
Receive data full interrupt (RXI) request and receive error interrupt (ERI) request
disabled*
Receive data full interrupt (RXI) request and receive error interrupt (ERI) request
enabled
Description
Transmission disabled*
Transmission enabled*
Description
Reception disabled*
Reception enabled*
2
1
2
1
(Initial value)
(Initial value)
(Initial value)