HD6432621 Hitachi, HD6432621 Datasheet - Page 39

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

16.2 Register Descriptions......................................................................................................... 585
16.3 Interface to Bus Master...................................................................................................... 591
16.4 Operation ........................................................................................................................... 592
16.5 Interrupts............................................................................................................................ 598
16.6 Usage Notes ....................................................................................................................... 598
Section 17 D/A Converter [Provided in the H8S/2626 Series only]
17.1 Overview............................................................................................................................ 603
17.2 Register Descriptions......................................................................................................... 606
17.3 Operation ........................................................................................................................... 609
Section 18 RAM
18.1 Overview............................................................................................................................ 611
18.2 Register Descriptions......................................................................................................... 612
18.3 Operation ........................................................................................................................... 613
18.4 Usage Notes ....................................................................................................................... 613
Section 19 ROM
19.1 Features.............................................................................................................................. 615
19.2 Overview............................................................................................................................ 616
16.1.1 Features ................................................................................................................ 581
16.1.2 Block Diagram...................................................................................................... 582
16.1.3 Pin Configuration ................................................................................................. 583
16.1.4 Register Configuration ......................................................................................... 584
16.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 585
16.2.2 A/D Control/Status Register (ADCSR)................................................................ 586
16.2.3 A/D Control Register (ADCR)............................................................................. 589
16.2.4 Module Stop Control Register A (MSTPCRA).................................................... 590
16.4.1 Single Mode (SCAN = 0) ..................................................................................... 592
16.4.2 Scan Mode (SCAN = 1) ....................................................................................... 594
16.4.3 Input Sampling and A/D Conversion Time.......................................................... 596
16.4.4 External Trigger Input Timing ............................................................................. 597
17.1.1 Features ................................................................................................................ 603
17.1.2 Block Diagram...................................................................................................... 604
17.1.3 Pin Configuration ................................................................................................. 605
17.1.4 Register Configuration ......................................................................................... 605
17.2.1 D/A Data Registers 2 and 3 (DADR2, DADR3).................................................. 606
17.2.2 D/A Control Register 23 (DACR23).................................................................... 606
17.2.3 Module Stop Control Register C (MSTPCRC).................................................... 608
18.1.1 Block Diagram...................................................................................................... 611
18.1.2 Register Configuration ......................................................................................... 612
18.2.1 System Control Register (SYSCR) ...................................................................... 612
19.2.1 Block Diagram...................................................................................................... 616
................................................................................................................... 611
................................................................................................................... 615
.................... 603
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