HD6432621 Hitachi, HD6432621 Datasheet - Page 601

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

15.3.2
After a hardware reset, the following initialization processing should be carried out:
These initial settings must be made while the HCAN is in bit configuration mode. Configuration
mode is a state in which the reset request bit (MCR0) in the master control register (MCR) is 1 and
the reset status bit in the general status register (GSR) is also 1 (GSR3 = 1). Configuration mode is
exited by clearing the reset request bit in MCR to 0; when MCR0 is cleared to 0, the HCAN
automatically clears the reset state bit (GSR3) in the general status register (GSR). The power-up
sequence then begins, and communication with the CAN bus is possible as soon as the sequence
ends. The power-up sequence consists of the detection of 11 consecutive recessive bits.
IRR0 Clearing: The reset interrupt flag (IRR0) is always set after a reset or recovery from
software standby mode. As an HCAN interrupt is initiated immediately when interrupts are
enabled, IRR0 should be cleared.
Bit Rate and Bit Timing Settings: As bit rate settings, a baud rate setting and bit timing setting
must be made each time a CAN node begins communication. The baud rate and bit timing settings
are made in the bit configuration register (BCR).
a. Note
Clearing of IRR0 bit in interrupt register (IRR)
Bit rate setting
Mailbox transmit/receive settings
Mailbox (RAM) initialization
Message transmission method setting
BCR can be written to at all times, but should only be modified in configuration mode.
Settings should be made so that all CAN controllers connected to the CAN bus have the same
baud rate and bit width.
Refer to table 15-3 for the range of values that can be used as settings (TSEG1, TSEG2, BRP,
sample point, and SJW) for BCR.
Initialization after Hardware Reset
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