HD6432621 Hitachi, HD6432621 Datasheet - Page 487
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HD6432621
Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
1.HD6432621.pdf
(1069 pages)
- Current page: 487 of 1069
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13.2.9
SCMR selects LSB-first or MSB-first by means of bit SDIR. Except in the case of asynchronous
mode 7-bit data, LSB-first or MSB-first can be selected regardless of the serial communication
mode. The descriptions in this chapter refer to LSB-first transfer.
For details of the other bits in SCMR, see 14.2.1, Smart Card Mode Register (SCMR).
SCMR is initialized to H'F2 by a reset and in hardware standby mode. It retains its previous state
in module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode.
Bits 7 to 4—Reserved: These bits are always read as 1 and cannot be modified.
Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion
format.
This bit is valid when 8-bit data is used as the transmit/receive format.
Bit 3
SDIR
0
1
Bit
Initial value
R/W
Smart Card Mode Register (SCMR)
Description
TDR contents are transmitted LSB-first
Receive data is stored in RDR LSB-first
TDR contents are transmitted MSB-first
Receive data is stored in RDR MSB-first
:
:
:
—
—
7
1
—
—
6
1
—
—
5
1
—
—
4
1
SDIR
R/W
3
0
SINV
R/W
2
0
—
—
1
1
(Initial value)
SMIF
R/W
0
0
443
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