HD6432621 Hitachi, HD6432621 Datasheet - Page 641
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HD6432621
Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
1.HD6432621.pdf
(1069 pages)
- Current page: 641 of 1069
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Table 16-4 A/D Conversion Time (Single Mode)
Item
A/D conversion start delay t
Input sampling time
A/D conversion time
Note: Values in the table are the number of states.
Table 16-5 A/D Conversion Time (Scan Mode)
CKS1
0
1
16.4.4
A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as if the ADST bit has been set to 1 by software. Figure 16-6 shows the
timing.
ø
ADTRG
ADST
Internal trigger signal
External Trigger Input Timing
CKS0
0
1
0
1
Conversion Time (State)
512 (Fixed)
256 (Fixed)
128 (Fixed)
64 (Fixed)
Figure 16-6 External Trigger Input Timing
Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max
t
t
D
SPL
CONV
18
—
515 —
CKS0 = 0
—
127 —
33
530 259 —
CKS1 = 0
10
—
CKS0 = 1
—
63
17
—
266 131 —
A/D conversion
6
—
CKS0 = 0
—
31
9
—
134 67
CKS1 = 0
4
—
CKS0 = 1
—
15
—
5
—
68
597
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