HD6432621 Hitachi, HD6432621 Datasheet - Page 90

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Type
Arithmetic
operations
46
Instruction
DIVXS
CMP
NEG
EXTU
EXTS
TAS
MAC
CLRMAC
LDMAC
STMAC
Size*
B/W
B/W/L
B/W/L
W/L
W/L
B
—
—
L
1
Function
Rd ÷ Rs
Performs signed division on data in two general
registers: either 16 bits ÷ 8 bits
remainder or 32 bits ÷ 16 bits
bit remainder.
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another
general register or with immediate data, and sets CCR
bits according to the result.
0 – Rd
Takes the two's complement (arithmetic complement) of
data in a general register.
Rd (zero extension)
Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by padding with zeros on the left.
Rd (sign extension)
Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by extending the sign bit.
@ERd – 0, 1
Tests memory contents, and sets the most significant bit
(bit 7) to 1.
(EAs)
Performs signed multiplication on memory contents and
adds the result to the multiply-accumulate register. The
following operations can be performed:
16 bits
16 bits
0
Clears the multiply-accumulate register to zero.
Rs
Transfers data between a general register and a
multiply-accumulate register.
MAC
MAC, MAC
(EAd) + MAC
16 bits + 32 bits
16 bits + 42 bits
Rd
Rd
(<bit 7> of @ERd)*
Rd
Rd
Rd
MAC
32 bits, saturating
42 bits, non-saturating
16-bit quotient and 16-
8-bit quotient and 8-bit
2