HD6432621 Hitachi, HD6432621 Datasheet - Page 621

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HD6432621

Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
Table 15-5 HCAN Interrupt Sources
IPR Bits
IPRM (6–4)
IPRM (2–0)
15.3.8
The DTC can be activated by reception of a message in the HCAN’s mailbox 0. When DTC
transfer ends after DTC activation has been set, the RXPR0 and RFPR0 flags are acknowledge
signal automatically. An interrupt request due to a receive interrupt from the HCAN cannot be sent
to the CPU in this case. Figure 15-13 shows a DTC transfer flowchart.
DTC Interface
Vector
ERS0
OVR0
RM0
RM1
SLE0
Vector Number IRR Bit
104
105
106
107
108
IRR5
IRR6
IRR0
IRR2
IRR3
IRR4
IRR7
IRR9
IRR12
IRR1
IRR1
IRR8
Description
Error passive interrupt (TEC
128)
Bus off interrupt (TEC
Hardware reset processing interrupt
Remote frame reception interrupt
Error warning interrupt (TEC
Error warning interrupt (REC
Overload frame transmission interrupt/bus off
recovery interrupt (11 recessive bits
times)
Unread message overwrite interrupt
HCAN sleep mode CAN bus operation
interrupt
Mailbox 0 message reception interrupt
Mailbox 1-15 message reception interrupt
Message transmission/cancellation interrupt
256)
128 or REC
96)
96)
128
577

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