HD6432621 Hitachi, HD6432621 Datasheet - Page 428
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HD6432621
Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
1.HD6432621.pdf
(1069 pages)
- Current page: 428 of 1069
- Download datasheet (5Mb)
11.2.7
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 1.
Port 1 is multiplexed with pins PO15 to PO8. Bits corresponding to pins used for PPG output must
be set to 1. For further information about P1DDR, see section 9.2, Port 1.
11.2.8
MSTPCRA is a 16-bit readable/writable register that performs module stop mode control.
When the MSTPA3 bit in MSTPCRA is set to 1, PPG operation stops at the end of the bus cycle
and a transition is made to module stop mode. Registers cannot be read or written to in module
stop mode. For details, see sections 21A.5, 21B.5, Module Stop Mode.
MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 3—Module Stop (MSTPA3): Specifies the PPG module stop mode.
Bit 3
MSTPA3
0
1
384
Bit
Initial value :
R/W
Bit
Initial value :
R/W
Port 1 Data Direction Register (P1DDR)
Module Stop Control Register A (MSTPCRA)
Description
PPG module stop mode cleared
PPG module stop mode set
:
:
:
:
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0
R/W
W
7
0
7
0
R/W
W
6
0
6
0
R/W
W
5
0
5
1
R/W
W
4
0
4
1
R/W
W
3
0
3
1
R/W
W
2
0
2
1
R/W
W
1
0
1
1
(Initial value)
R/W
W
0
0
0
1
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