HD6432621 Hitachi, HD6432621 Datasheet - Page 599

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Notes: *1 When IRR0 is set to 1 (automatically) due to a hardware reset*
LAFM setting (receive identifier mask setting)
Message transmission method initialization
MC[x] setting (receive identifier setting)
MBIMR setting (interrupt mask setting)
IMR setting (interrupt mask setting)
CAN bus communication enabled
*2 In a reset and in hardware standby mode, the module stop bit is initialized to 1 and
Initialization of HCAN module
Mailbox (RAM) initialization
recessive bits received?
initiated reset processing" interrupt is generated.
the HCAN enters the module stop state.
IRR0 = 1 (automatic)*
MCR0 = 1 (automatic)
GSR3 = 1 (automatic)
Hardware reset
GSR3 = 0 & 11
MBCR setting
BCR setting
Clear IRR0
GSR3 = 0?
MCR0 = 0
Yes
Yes
Figure 15-4 Hardware Reset Flowchart
1
No
No
Bit configuration mode
Period in which BCR, MBCR, etc.,
are initialized
: Settings by user
: Processing by hardware
2
, a "hardware reset
555