HD6432621 Hitachi, HD6432621 Datasheet - Page 548

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HD6432621

Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
14.3.5
Only an internal clock generated by the on-chip baud rate generator can be used as the
transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1,
CKS0, BCP1 and BCP0 bits in SMR. The formula for calculating the bit rate is as shown below.
Table 14-5 shows some sample bit rates.
If clock output is selected by setting CKE0 to 1, a clock is output from the SCK pin. The clock
frequency is determined by the bit rate and the setting of bits BCP1 and BCP0.
B =
Where: N = Value set in BRR (0 N 255)
Table 14-4 Correspondence between n and CKS1, CKS0
n
0
1
2
3
Table 14-5 Examples of Bit Rate B (bit/s) for Various BRR Settings
N
0
1
2
Note: Bit rates are rounded to the nearest whole number.
504
B = Bit rate (bit/s)
ø = Operating frequency (MHz)
n = See table 14-4
S = Number of internal clocks in 1-bit period, set by BCP1 and BCP0
Clock
10.00
13441
6720
4480
S 2
(When n = 0 and S = 372)
CKS1
0
1
2n+1
ø
(N + 1)
10.714
14400
7200
4800
CKS0
0
1
0
1
13.00
17473
8737
5824
10
6
14.285
19200
9600
6400
ø (MHz)
16.00
21505
10753
7168
18.00
24194
12097
8065
20.00
26882
13441
8961

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