HD6432621 Hitachi, HD6432621 Datasheet - Page 16

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Section
15.5 Usage Notes
8. Using bit operation
instructions
9. HTxD pin output in
error passive state
10. Transition to
HCAN sleep mode
11. Message
transmission
cancellation (TxCR)
12. TxCR in the bus
off state
19.11.2 Programmer
Mode Operation
Table 19-11 Settings
for Various Operating
Modes in Programmer
Mode
Page
580
656
Description
Newly added
8. Using bit operation instructions
Start flags in HCAN are cleared by writing 1 to them; there is no need to use
bit operation instructions to clear them. To clear a flag, use the MOV
instruction to write a 1 to the bit to be cleared.
9. HTxD pin output in error passive state
If the HRxD pin becomes fixed at 1 during message transmission or
reception when the HCAN is in the error active state, the HTxD pin will
output 0 continuously while in the error passive state. To stop continuous 0
output to the CAN bus, disable the HCAN by means of an error warning
interrupt or by setting the HCAN module stop mode through detection of a
fixed 1 state by the HxRD pin monitor.
10. Transition to HCAN sleep mode
The HCAN stops (transmission/reception stops) when MCR0 is cleared to 0
immediately after an HCAN sleep mode transition effected by setting TXPR
of the HCAN to 1 and setting MCR5 to 1. When a transition is made to the
HCAN sleep mode by means of the above steps, a 10-cycle wait should be
inserted after the TxPR setting. After an HCAN sleep mode transition,
release the HCAN sleep mode by clearing MCR5 to 0.
11. Message transmission cancellation (TxCR)
If all the following conditions are met when cancellation of a transmission
message is performed by means of TxCR of the HCAN, the TxCR or TxPR
bit indicating cancellation is not cleared even though internal transmission is
canceled.
When canceling a message using TxCR, 1 should be written continuously
until TxCR or TxPR becomes 0.
12. TxCR in the bus off state
If TxPR is set before the HCAN goes to the bus off state, and a transition is
made to the bus off state with transmission incomplete, cancellation will be
performed even if TxCR is set during the bus off period, and the message
will be transmitted after a transition to the error active state.
Mode
Read
Output disable
Command write
Chip disable*
1
FWE
H or L
H or L
H or L*
H or L
3
CE
L
L
L
H
OE
L
H
H
X
Pin Names
WE
H
H
L
X
I/O7– I/O0
Data output
Hi-Z
Data input
Hi-Z
A18–A0
Ain
X
Ain*
X
2