HD6432621 Hitachi, HD6432621 Datasheet - Page 175

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

(4) When the SLEEP instruction causes a transition to software standby mode or watch mode:
6.3.5
If a PC break interrupt is generated when the following operations are being performed, exception
handling is executed on completion of the specified transfer.
(1) When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction:
(2) When a PC break interrupt is generated at a DTC transfer address:
Note: * Supported only in the H8S/2626 Series.
Execution of instruction
after sleep instruction
PC break exception
SLEEP instruction
After execution of the SLEEP instruction, and following the clock oscillation settling time, a
transition is made to high-speed (medium-speed) mode via direct transition exception
handling. After the transition, PC break interrupt handling is executed, then the instruction at
the address after the SLEEP instruction is executed (figure 6-2 (C)) (Supported only in the
H8S/2626 Series).
After execution of the SLEEP instruction, a transition is made to the respective mode, and PC
break interrupt handling is not executed. However, the CMFA or CMFB flag is set (figure 6-2
(D)).
PC break exception handling is executed after all data transfers have been completed and the
EEPMOV.B instruction has ended.
PC break exception handling is executed after the DTC has completed the specified number of
data transfers, or after data for which the DISEL bit is set to 1 has been transferred.
execution
handling
(A)
PC Break Operation in Continuous Data Transfer
Figure 6-2 Operation in Power-Down Mode Transitions
Execution of instruction
after sleep instruction
PC break exception
exception handling
SLEEP instruction
Direct transition
System clock
execution
handling
subclock
(B)*
Subactive
mode
Execution of instruction
oscillation settling time
after sleep instruction
PC break exception
exception handling
SLEEP instruction
Direct transition
system clock,
Subclock
execution
handling
(C)*
High-speed
(medium-speed)
mode
SLEEP instruction
respective mode
Transition to
execution
(D)
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