HD6432621 Hitachi, HD6432621 Datasheet - Page 951

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

TSR3—Timer Status Register 3
Note: * Can only be written with 0 for flag clearing.
Bit
Initial value
Read/Write
:
:
:
—
—
7
1
Overflow flag
0 [Clearing condition]
1
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000)
TGRD input capture/output compare flag
0 [Clearing conditions]
1
—
—
6
1
• When DTC is activated by TGID interrupt, and DISEL bit in DTC’s MRB is 0
• When 0 is written to TGFD after reading TGFD = 1
[Setting conditions]
• When TCNT = TGRD while TGRD is functioning as output compare register
• When TCNT value is transferred to TGRD by input capture signal while
TGRD is functioning as input capture register
TGRC input capture/output compare flag
0 [Clearing conditions]
1
• When DTC is activated by TGIC interrupt, and DISEL bit in DTC’s MRB is 0
• When 0 is written to TGFC after reading TGFC = 1
[Setting conditions]
• When TCNT = TGRC while TGRC is functioning as output compare register
• When TCNT value is transferred to TGRC by input capture signal while
TGRC is functioning as input capture register
—
—
5
0
TGRB input capture/output compare flag
0 [Clearing conditions]
1
• When DTC is activated by TGIB interrupt, and DISEL
• When 0 is written to TGFB after reading TGFB = 1
[Setting conditions]
• When TCNT = TGRB while TGRB is functioning as
• When TCNT value is transferred to TGRB by input
R/(W)*
TCFV
bit in DTC’s MRB is 0
output compare register
capture signal while TGRB is functioning as input
capture register
4
0
TGRA input capture/output compare flag
0
1
H'FE85
[Clearing conditions]
• When DTC is activated by TGIA interrupt, and DISEL
• When 0 is written to TGFA after reading TGFA = 1
[Setting conditions]
• When TCNT = TGRA while TGRA is functioning as
• When TCNT value is transferred to TGRA by input
bit in DTC’s MRB is 0
output compare register
capture signal while TGRA is functioning as input
capture register
R/(W)*
TGFD
3
0
R/(W)*
TGFC
2
0
R/(W)*
TGFB
1
0
R/(W)*
TGFA
0
0
TPU3
907