HD6432621 Hitachi, HD6432621 Datasheet - Page 23
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HD6432621
Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
1.HD6432621.pdf
(1069 pages)
- Current page: 23 of 1069
- Download datasheet (5Mb)
Section
A.1 Instruction List
Table A-1 Instruction
Set
A.2 Instruction Codes
Table A-2 Instruction
Codes
A.3 Operation Code
Map
Table A-3 Operation
Code Map (1), (2)
A.4 Number of States
Required for Instruction
Execution
Table A-5 Number of
Cycles in Instruction
Execution
A.5 Bus States during
Instruction Execution
Page
775
785
791
800,
801,
804,
805
811,
813,
817 to
819
815,
818
Description
Notes amended
[6]
[7]
[8]
[9]
[10]
[11]
Table amended
Note added
Note: * Cannot be used in the H8S/2626 Series and H8S/2623 Series.
Normal mode deleted
Normal mode deleted
Table amended
MOVFPE
MOVTPE
MOVFPE @aa:16,Rd
MOVTPE Rs,@aa:16
STMAC MACH,ERd
Instruction
Set to 1 when the divisor is negative; otherwise cleared to 0.
Set to 1 when the divisor is zero; otherwise cleared to 0.
Set to 1 when the quotient is negative; otherwise cleared to 0.
One additional state is required for execution when EXR is valid.
MAC instruction results are indicated in the flags when the STMAC
instruction is executed.
A maximum of three additional states are required for execution of
one of these instructions within three states after execution of a MAC
instruction. For example, if there is a one-state instruction (such as
NOP) between a MAC instruction and one of these instructions, that
instruction will be two states longer.
MOVFPE @aa:16,Rd
MOVTPE Rs,@aa:16
*
*
4
4
R:W NEXT
Cannot be used in the H8S/2626 Series or H8S/2623 Series.
1
B
B
Cannot be used in the H8S/2626 Series or H8S/2623 Series.
2
3
4
5
6
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