HD6432621 Hitachi, HD6432621 Datasheet - Page 41

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HD6432621

Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
Section 20 Clock Pulse Generator
20.1 Overview............................................................................................................................ 675
20.2 Register Descriptions......................................................................................................... 677
20.3 Oscillator............................................................................................................................ 679
20.4 PLL Circuit........................................................................................................................ 684
20.5 Medium-Speed Clock Divider........................................................................................... 684
20.6 Bus Master Clock Selection Circuit .................................................................................. 684
20.7 Subclock Oscillator (H8S/2626 Series Only).................................................................... 685
20.8 Subclock Waveform Shaping Circuit (H8S/2626 Series Only) ........................................ 686
20.9 Note on Crystal Resonator................................................................................................. 686
Section 21A Power-Down Modes [H8S/2623 Series]
21A.1 Overview ........................................................................................................................ 687
21A.2 Register Descriptions...................................................................................................... 690
21A.3 Medium-Speed Mode ..................................................................................................... 695
21A.4 Sleep Mode..................................................................................................................... 696
21A.5 Module Stop Mode ......................................................................................................... 696
21A.6 Software Standby Mode ................................................................................................. 698
21A.7 Hardware Standby Mode................................................................................................ 701
21A.8 ø Clock Output Disabling Function................................................................................ 702
20.1.1 Block Diagram...................................................................................................... 676
20.1.2 Register Configuration ......................................................................................... 676
20.2.1 System Clock Control Register (SCKCR) ........................................................... 677
20.2.2 Low-Power Control Register (LPWRCR)............................................................ 678
20.3.1 Connecting a Crystal Resonator ........................................................................... 679
20.3.2 External Clock Input ............................................................................................ 682
21A.1.1 Register Configuration ................................................................................... 690
21A.2.1 Standby Control Register (SBYCR) .............................................................. 690
21A.2.2 System Clock Control Register (SCKCR) ..................................................... 692
21A.2.3 Low-Power Control Register (LPWRCR)...................................................... 693
21A.2.4 Module Stop Control Register (MSTPCR) .................................................... 694
21A.4.1 Sleep Mode..................................................................................................... 696
21A.4.2 Exiting Sleep Mode........................................................................................ 696
21A.5.1 Module Stop Mode ......................................................................................... 696
21A.5.2 Usage Notes.................................................................................................... 698
21A.6.1 Software Standby Mode ................................................................................. 698
21A.6.2 Clearing Software Standby Mode .................................................................. 698
21A.6.3 Setting Oscillation Stabilization Time after Clearing Software
21A.6.4 Software Standby Mode Application Example .............................................. 700
21A.6.5 Usage Notes.................................................................................................... 701
21A.7.1 Hardware Standby Mode................................................................................ 701
21A.7.2 Hardware Standby Mode Timing ................................................................... 702
Standby Mode ................................................................................................ 699
.................................................................................. 675
............................................. 687
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