HD6432621 Hitachi, HD6432621 Datasheet - Page 11

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Section
12.5.6 OVF Flag
Clearing in Interval
Timer Mode
13.2.8 Bit Rate
Register (BRR)
Table 13-3 BRR
Settings for Various Bit
Rates (Asynchronous
Mode)
Table 13-4 BRR
Settings for Various Bit
Rates (Clocked
Synchronous Mode)
Table 13-5 Maximum
Bit Rate for Each
Frequency
(Asynchronous Mode)
Table 13-6 Maximum
Bit Rate with External
Clock Input
(Asynchronous Mode)
Table 13-7 Maximum
Bit Rate with External
Clock Input (Clocked
Synchronous Mode)
15.2.2 General Status
Register (GSR)
15.2.3 Bit
Configuration Register
(BCR)
Page
416
436
439
441
442
442
525
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Description
Newly added
12.5.6 OVF Flag Clearing in Interval Timer Mode
When the OVF Flag setting conflicts with the OVF flag reading in interval
timer mode, writing 0 to the OVF bit may not clear the flag even though the
OVF bit has been read while it is 1. If there is a possibility that the OVF flag
setting and reading will conflict, such as when the OVF flag is polled with the
interval timer interrupt disabled, read the OVF bit while it is 1 at least twice
before writing 0 to the OVF bit to clear the flag.
2 MHz, 2.097152 MHz, 2.4576 MHz, 3 MHz, and 3.6864 MHz columns of
table deleted
2 MHz column of table deleted
2 MHz, 2.097152 MHz, 2.4576 MHz, 3 MHz, and 3.6864 MHz rows of table
deleted
2 MHz, 2.097152 MHz, 2.4576 MHz, 3 MHz, and 3.6864 MHz rows of table
deleted
2 MHz row of table deleted
7th line changed as follows
The general status register (GSR) is an 8-bit readable register that indicates
the status of the CAN bus.
9th line changed as follows
Bits 7 to 4—Reserved: These bits always read 0.
15.3.2 Initialization after Hardware Reset
Detailed Description of One Bit of figure,
HCAN bit rate calculation,
BCR Setting Constraints,
Setting Range for TSEG1 and TSEG2 in BCR of table
Moved to Bit Rate and Bit Timing Settings