HD6432621 Hitachi, HD6432621 Datasheet - Page 120

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.
Bit 3
NMIEG
0
1
Bit 2—Reserved: Only 0 should be written to this bit.
Bit 1—Reserved: This bit is always read as 0 and cannot be modified.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset status is released. It is not initialized in software standby mode.
Bit 0
RAME
0
1
Note: When the DTC is used, the RAME bit must be set to 1.
3.2.3
PFCR is an 8-bit readable/writable register that performs address output control in external
expanded mode.
PFCR is initialized to H'0D/H'00 by a reset and in hardware standby mode. It retains its previous
state in software standby mode.
Bits 7 to 4—Reserved: Only 0 should be written to these bits.
Bit 5—BUZZE Output Enable (BUZZE): This bit is for use only in the H8S/2626. Only 0
should be writtn to this bit.
Bits 3 to 0—Address Output Enable 3 to 0 (AE3 to AE0): These bits select enabling or
disabling of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When
a pin is enabled for address output, the address is output regardless of the corresponding DDR
76
Bit
Initial value
R/W
Pin Function Control Register (PFCR)
Description
An interrupt is requested at the falling edge of NMI input
An interrupt is requested at the rising edge of NMI input
Description
On-chip RAM is disabled
On-chip RAM is enabled
:
:
:
R/W
—
7
0
R/W
—
6
0
BUZZE
R/W
5
0
R/W
—
4
0
R/W
AE3
1/0
3
R/W
AE2
1/0
2
R/W
AE1
1
0
(Initial value)
(Initial value)
AE0
R/W
1/0
0