HD6432621 Hitachi, HD6432621 Datasheet - Page 633

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HD6432621

Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
16.2.3
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D
conversion operations and sets the A/D conversion time.
ADCR is initialized to H'33 by a reset, and in standby mode or module stop mode.
Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): Select enabling or disabling of
the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion
is stopped (ADST = 0).
Bit 7
TRGS1
0
1
Bits 5, 4, 1, and 0—Reserved: These bits are always read as 1 and cannot be modified.
Bits 3 and 2—Clock Select 1 and 0 (CKS1, CKS0): These bits select the A/D conversion time.
The conversion time should be changed only when ADST = 0. Make a setting that gives a value
not lower than that shown in table 22-8.
Bit 3
CKS1
0
1
Bit
Initial value
R/W
A/D Control Register (ADCR)
Bit 6
TRGS0
0
1
0
1
Bit 2
CKS0
0
1
0
1
:
:
:
TRGS1
R/W
7
0
Description
A/D conversion start by software is enabled
A/D conversion start by TPU conversion start trigger is enabled
Setting prohibited
A/D conversion start by external trigger pin (ADTRG) is enabled
Description
Conversion time = 530 states (max.)
Conversion time = 266 states (max.)
Conversion time = 134 states (max.)
Conversion time = 68 states (max.)
TRGS0
R/W
6
0
5
1
4
1
CKS1
R/W
3
0
CKS0
R/W
2
0
1
1
(Initial value)
(Initial value)
0
1
589

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