HD6432621 Hitachi, HD6432621 Datasheet - Page 688

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

644
Notes: *1 Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be
Number of Writes
tspsu:
Write pulse application subroutine
tcp:
Wait (z0) s or (z1) s or (z2) s
Clear PSU1 bit in FLMCR1
N1+N2–2
N1+N2–1
Set PSU1 bit in FLMCR1
Sub-Routine Write Pulse
tsp10 or tsp30 or tsp200:
N1+N2
Clear P1 bit in FLMCR1
N1–1
N1+1
N1+2
N1+3
Set P1 bit in FLMCR1
*2 Verify data is read in 16-bit (word) units.
*3 Even bits for which programming has been completed in the 128-byte programming loop will be subject to programming again if they fail the
*4 A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional-programming
*5 A write pulse of 30 s or 200 s is applied according to the progress of the programming operation. See Note *6 for details of the pulse widths.
N1
1
2
data storage area (128 bytes)
·
·
·
·
·
·
Reprogram data storage
Note *6: Programming Time
Additional-programming
performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
subsequent verify operation.
data must be provided in RAM. The reprogram and additional-programming data contents are modified as programming proceeds.
When writing of additional-programming data is executed, a 10 s write pulse should be applied. Reprogram data X' means reprogram data when
the write pulse is applied.
Disable WDT
Program data storage
Reprogram Data Computation Table
Additional-Programming Data Computation Table
Enable WDT
Original Data (D)
Wait ( ) s
Wait (y) s
Wait ( ) s
End Sub
area (128 bytes)
area (128 bytes)
Reprogram Data (X')
RAM
Programming
0
0
1
1
P1 Bit Set Time ( s)
0
0
1
1
z0
z0
z0
z0
z2
z2
z2
z2
z2
z2
·
·
·
·
·
·
Figure 19-11 Program/Program-Verify Flowchart
Verify Data (V)
*
Programming
5
Additional
z1
z1
z1
z1
0
1
0
1
—
—
—
—
—
—
·
·
·
·
·
·
Verify Data (V)
0
1
0
1
Increment address
Reprogram Data (X)
Additional-Programming Data (X)
1
0
1
1
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
Transfer reprogram data to reprogram data area
NG
Store 128 bytes of program data in program
Additional-programming data computation
Transfer additional-programming data to
Successively write 128-byte reprogram
tsswe:
tcpv:
tcswe:
tspv:
tspur:
H'FF dummy write to verify address
tcpv:
tcswe:
data area and reprogram data area
Additional programming subroutine
additional-programming data area
Programming complete
Programming is incomplete: reprogramming should be performed
Left in the erased state
0
1
1
1
Write pulse application subroutine
Reprogram data computation
Clear SWE1 bit in FLMCR1
Set SWE1 bit in FLMCR1
Clear PV1 bit in FLMCR1
Set PV1 bit in FLMCR1
verification completed?
Start of programming
data to flash memory
End of programming
Read verify data
Program data =
128-byte data
Wait ( 0) s
Wait ( 1) s
verify data?
Wait ( ) s
Wait ( ) s
Wait ( ) s
OK
OK
N1
N1
START
m = 0 ?
m = 0
n = 1
n ?
n ?
Sub-Routine-Call
Sub-Routine-Call
OK
OK
Additional programming should be performed
Additional programming should not be performed
Additional programming should not be performed
Additional programming should not be performed
Comments
NG
NG
NG
*
NG
*
*
2
3
Comments
5
Programming must be executed in the erased state.
Do not perform additional programming on addresses
that have already been programmed.
*
*
4
1
tcswe:
*
m = 1
1
Clear SWE1 bit in FLMCR1
*
*
4
4
Programming failure
n
Wait ( 1) s
(N1 + N2) ?
OK
NG
n
n + 1