HD6432621 Hitachi, HD6432621 Datasheet - Page 475

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HD6432621

Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
13.2.7
Note: * Only 0 can be written, for flag clearing.
SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and
multiprocessor bits.
SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags
TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be
read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified.
SSR is initialized to H'84 by a reset, in standby mode, watch mode, subactive mode, subsleep
mode, or module stop mode.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from
TDR to TSR and the next serial data can be written to TDR.
Bit 7
TDRE
0
1
Bit
Initial value
R/W
Serial Status Register (SSR)
Description
[Clearing conditions]
[Setting conditions]
:
:
:
When 0 is written to TDRE after reading TDRE = 1
When the DTC is activated by a TXI interrupt and writes data to TDR
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and data can be written to TDR
R/(W)*
TDRE
7
1
R/(W)*
RDRF
6
0
R/(W)*
ORER
5
0
R/(W)*
FER
4
0
R/(W)*
PER
3
0
TEND
R
2
1
MPB
R
1
0
(Initial value)
MPBT
R/W
0
0
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