UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 1067

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3rd
Edition
Modification of Figure 14-1 Block Diagram of D/A Converter
Addition of 15.2.1 Pin functions of each channel
Addition of a note for Figure 15-7 Continuous Transmission Processing
Modification of 16.1 Features
Addition of 16.2.1 Pin functions of each channel
Addition of Note to Figure 16-11 Single Transfer Mode Operation (Slave Mode,
Transmission Mode)
Addition of Note to Figure 16-13 Single Transfer Mode Operation (Slave Mode,
Reception Mode)
Addition of Note to Figure 16-15 Single Transfer Mode Operation (Slave Mode,
Transmission/Reception Mode)
Modification of Figure 16-19 Continuous Transfer Mode Operation (Master Mode,
Reception Mode)
Modification of Figure 16-21 Continuous Transfer Mode Operation (Master Mode,
Transmission/Reception Mode)
Addition of Note to Figure 16-23 Continuous Transfer Mode Operation (Slave Mode,
Transmission Mode)
Modification of Figure 16-25 Continuous Transfer Mode Operation (Slave Mode,
Reception Mode)
Modification of Figure 16-27 Continuous Transfer Mode Operation (Slave Mode,
Transmission/Reception Mode)
Modification of 18.13 (4) (a) Temporarily stop transfer of all DMA channels
Addition of 20.2 Pin Functions
Modification of Caution 2 in 21.4.1 Setting and operation status
Modification of Caution 2 in 21.5.1 Setting and operation status
Modification of Caution 2 in 21.6.1 Setting and operation status
Modification of Caution 2 in 21.8.1 Setting and operation status
Modification of Figure 22-7 Reset Function Operation Flow
Modification of Figure 23-1 Block Diagram of Clock Monitor
Modification of Figure 24-2 Operation Timing of Low-Voltage Detector (LVIMD Bit = 1,
Low-Voltage Detection Level: 2.80 V)
Modification of Figure 24-3 Operation Timing of Low-Voltage Detector (LVIMD Bit = 0,
Low-Voltage Detection Level: 2.80 V)
Modification of Note 3 in Figure 29-4 Circuit Connection Example When
UARTA0/CSIB0/CSIB3 Is Used for Communication Interface
Addition of 121-PIN PLASTIC FBGA (8 × 8) to CHAPTER 31 PACKAGE DRAWINGS
APPENDIX E REVISION HISTORY
User’s Manual U18953EJ5V0UD
Description
CHAPTER 14 D/A
CONVERTER
CHAPTER 15
ASYNCHRONOUS
SERIAL INTERFACE
A (UARTA)
CHAPTER 16
CLOCKED SERIAL
INTERFACE B
(CSIB)
CHAPTER 18 DMA
FUNCTION (DMA
CONTROLLER)
CHAPTER 20 KEY
INTERRUPT
FUNCTION
CHAPTER 21
STANDBY
FUNCTION
CHAPTER 22
RESET FUNCTION
CHAPTER 23
CLOCK MONITOR
CHAPTER 24 LOW-
VOLTAGE
DETECTOR (LVI)
CHAPTER 29 ON-
CHIP DEBUG
FUNCTION
CHAPTER 31
PACKAGE
DRAWINGS
Applied to:
1065
(3/6)