UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 183

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.6.2
port/alternate functions, the value of the output latch of an input port that is not subject to manipulation may be written
in addition to the targeted bit.
P91 to P97
When a 1-bit manipulation instruction is executed on a port that provides both input and output functions or
Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
<Example>
Port 9L latch
0
Cautions on bit manipulation instruction for port n register (Pn)
P90
0
0
When the P90 pin is an output pin, the P91 to P97 pins are input pins (the status of all pins is high
level), and the value of the port latch is 00H, if the output of the P90 pin is changed from low level to
high level via a bit manipulation instruction, the value of the port latch is FFH.
Explanation: When writing to and reading from the Pn register of a port whose PMnm bit is 1, the
output latch is written and the pin status is read.
A bit manipulation instruction is executed in the following order in the V850ES/JG3-L.
<1> The Pn register is read in 8-bit units.
<2> The targeted bit is manipulated.
<3> The Pn register is written in 8-bit units.
In step <1>, the value of the output latch (0) of the P90 pin, which is an output pin, is read, while the
pin statuses of the P91 to P97 pins, which are input pins, are read. If the pin statuses of the P91 to
P97 pins are high level at this time, the value read is FEH.
The value is changed to FFH by the manipulation in <2>.
FFH is written to the output latch by the manipulation in <3>.
0
Pin status: High level
Bit manipulation instruction for P90 bit
<1> The P9L register is read in 8-bit units.
<2> Set (1) to the P90 bit.
<3> Write the results of <2> to the output latch of the P9L register in 8-bit units.
Low-level output
0
Figure 4-36. Bit Manipulation Instruction (P90 Pin)
• In the case of P90, an output pin, the value of the port latch (0) is read.
• In the case of P91 to P97, input pins, the pin status (1) is read.
0
0
CHAPTER 4 PORT FUNCTIONS
0
User’s Manual U18953EJ5V0UD
Bit manipulation
instruction
(set1 0, P9L[r0])
is executed for
P90 bit.
P91 to P97
Port 9L latch
1
P90
1
1
1
Pin status: High level
High-level output
1
1
1
1
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