UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 774

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.9 DMA Transfer Start Factors
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There are two types of DMA transfer start factors, as shown below.
(1) Request by software
(2) Request by on-chip peripheral I/O
If the DCHCn.STGn bit is set to 1 while the DCHCn.TCn bit is 0 and DCHCn.Enn bit is 1 (DMA transfer
enabled), DMA transfer starts.
To request the next DMA transfer cycle immediately after that, confirm, by using the DBCn register, that the
preceding DMA transfer cycle has been completed, and set the STGn bit to 1 again (n = 0 to 3).
If an interrupt request is generated from the on-chip peripheral I/O set by the DTFRn register when the TCn bit
is 0 and Enn bit is 1 (DMA transfer enabled), DMA transfer starts (n = 0 to 3).
Cautions 1. Two start factors (software trigger and hardware trigger) cannot be used for one DMA
TCn bit = 0, Enn bit = 1
STGn bit = 1 … Starts the first DMA transfer.
Confirm that the contents of the DBCn register have been updated.
STGn bit = 1 … Starts the second DMA transfer.
Generation of terminal count … Enn bit = 0, TCn bit = 1, and INTDMAn signal is generated.
2. A new transfer request generated for a DMA channel after the preceding DMA transfer
3. The transfer request interval for the same DMA channel varies depending on the setting
channel. If two start factors are simultaneously generated for one DMA channel, only one
of them is valid. However, the valid start factor cannot be identified.
request was generated and before the transfer is complete is ignored (cleared).
of bus waits in the DMA transfer cycle, the start status of the other channels, or an
external bus hold request. In particular, as described in Caution 2, a new transfer request
generated for the same channel before a DMA transfer cycle starts or during a DMA
transfer cycle is ignored. Therefore, the transfer request interval for the same DMA
channel must be sufficiently secured by the system. When a software trigger is used,
whether the preceding DMA transfer cycle has completed can be checked by reading the
DBCn register.
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CHAPTER 20 DMA FUNCTION (DMA CONTROLLER)
User’s Manual U18953EJ5V0UD