UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 844

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

842
(1) Procedure for switching from normal mode to low-voltage STOP mode
Cautions 1. Insert five or more NOP instructions after the instruction that stores data in the PSC register
Specify the following settings in the normal operation mode (while the main clock is operating). In addition, set
up the OSTS register as necessary.
<1> Stop the functions whose operation is specified as stopped in Table 23-9 Operating Status in Low-
<2> Disable DMA.
<3> • Disable maskable interrupts by using the DI instruction.
<4> Write C9H (enabling data) to the REGPR register.
<5> Write 01H to the REGOVL0 register.
<6> Write 00H (protection data) to the REGPR register.
<7> As necessary, enable maskable interrupts, the NMI interrupt, or the INTWDT2 interrupt by using the EI
<8> Set the STOP mode.
Be sure to observe the above sequence.
Note, however, that step <7> may be performed at any time as long as it is done after step <6>. (The setting in
step <7> may be made without problem, even after the low-voltage STOP mode has been released.)
Voltage STOP Mode.
Be especially sure to stop the following, because they are signals from external sources.
• Stop the SCKBn input clock when the SCKBn input clock to CSIBn is selected (n = 0 to 4).
• Stop the ASCKA0 input clock when the ASCKA0 input clock to UARTA0 is selected.
• Disable the NMI interrupt (INTF02 = 0, INTR02 = 0).
• Create a status in which the INTWDT2 signal is not generated (create a status in which the INTWDT2
At this time, the output voltage of the regulator is at the normal level.
instruction (restore the settings in <2> and <3> above).
In the STOP mode, the output voltage of the regulator drops, decreasing the current consumption to an
extremely low level.
2. If the STOP mode/low-voltage STOP mode is set while an unmasked interrupt request signal
signal is not generated immediately after watchdog timer 2 has been cleared).
PSMR.PSM1, PSMR.PSM0 bits = 01 or 11
PSC.STP bit = 1
to set the STOP mode/low-voltage STOP mode.
is being held pending, the CPU does not shift to the STOP mode/low-voltage STOP mode but
executes the next instruction.
CHAPTER 23 STANDBY FUNCTION
User’s Manual U18953EJ5V0UD