UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 317

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(c) Processing an overflow when two capture registers are used
Care must be exercised in processing the overflow flag when two capture registers are used. First, an
example of incorrect processing is shown below.
The following problem may occur when two pulse widths are measured in the free-running timer mode.
<1> The TPnCCR0 register is read (the default value of the TIPn0 pin input is set).
<2> The TPnCCR1 register is read (the default value of the TIPn1 pin input is set).
<3> The TPnCCR0 register is read.
<4> The TPnCCR1 register is read.
When two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the
other capture register may not obtain the correct pulse width.
This problem can be resolved by using software, as shown in the example below.
Remark
Figure 7-60. Example of Incorrect Processing When Two Capture Registers Are Used
TPnCCR0 register
TPnCCR1 register
INTTPnOV signal
The TPnOVF bit is read. If the TPnOVF bit is 1, it is cleared to 0.
Because the TPnOVF bit is 1, the pulse width can be calculated by (10000H + D
The TPnOVF bit is read. Because the bit was cleared in <3>, 0 is read.
Because the TPnOVF bit is 0, the pulse width can be calculated by (D
TIPn0 pin input
TIPn1 pin input
16-bit counter
TPnOVF bit
n = 0 to 5
TPnCE bit
FFFFH
0000H
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
D
00
User’s Manual U18953EJ5V0UD
<1>
D
10
<2>
D
00
D
D
01
10
<3>
D
11
<4>
11
D
− D
01
10
) (incorrect).
D
11
01
− D
00
).
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