UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 610
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3738GF-GAS-AX
Manufacturer Part Number
UPD70F3738GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3737GF-GAS-AX.pdf
(1071 pages)
Specifications of UPD70F3738GF-GAS-AX
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3738GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Cautions 1. Be sure to read the UC0RX register even when a reception error occurs. If the UC0RX register
2. Reception is performed assuming that there is only one stop bit. A second stop bit is ignored.
3. When reception is completed, read the UC0RX register after the reception complete interrupt
4. If the receive completion processing (INTUC0R signal generation) of UARTC0 conflicts with
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (
is not read, an overrun error occurs during reception of the next data, and reception errors
continue occurring indefinitely.
request signal (INTUC0R) has been generated, and clear the UC0RXE bit to 0. If the UC0RXE
bit is cleared to 0 before the INTUC0R signal is generated, the read value of the UC0RX
register cannot be guaranteed.
setting the UC0PWR bit or UC0RXE bit to 0, the INTUC0R signal may be generated in spite of
there being no data stored in the UC0RX register.
To complete reception without waiting for INTUC0R signal generation, be sure to clear (0) the
interrupt request flag (UC0RIF) of the UC0RIC register, after setting (1) the interrupt mask flag
(UC0RMK) of the interrupt control register (UC0RIC) and then set (1) the UC0PWR bit or
UC0RXE bit to 0.
User’s Manual U18953EJ5V0UD
PD70F3792, 70F3793)
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