UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 589

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UPD70F3738GF-GAS-AX

Manufacturer Part Number
UPD70F3738GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3738GF-GAS-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3738GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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17.1 Features
The
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (
On-chip dedicated baud rate generator
Transfer rate: 300 bps to 625 kbps (using dedicated baud rate generator)
Full-duplex communication
Double buffer configuration Internal UARTC0 receive data register (UC0RX)
Reception error detection function
• Parity error
• Framing error
• Overrun error
Interrupt sources: 2
• Reception complete interrupt (INTUC0R):
• Transmission enable interrupt (INTUC0T):
Character length: 7 to 9 bits
Parity function: Odd, even, 0, none
Transmission stop bit: 1, 2 bits
MSB-/LSB-first transfer selectable
Internal digital noise filter
Inverted input/output of transmit/receive data possible
SBF (Sync Break Field) transmission/reception in the LIN (Local Interconnect Network) communication format
• 13 to 20 bits selectable for SBF transmission
• Recognition of 11 bits or more possible for SBF reception
• SBF reception flag provided
μ
PD70F3792, 70F3793 have a 1-channel UARTC.
Internal UARTC0 transmit data register (UC0TX)
User’s Manual U18953EJ5V0UD
This interrupt occurs upon transfer of receive data from the
receive shift register to the receive data register after serial
transfer completion, in the reception enabled status.
This interrupt occurs upon transfer of transmit data from the
transmit data register to the transmit shift register in the
transmission enabled status. (Continuous transmission is
possible.)
μ
PD70F3792, 70F3793)
587

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