UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 13

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 5 BUS CONTROL FUNCTION...........................................................................................183
CHAPTER 6 CLOCK GENERATOR .....................................................................................................213
4.4
4.5
4.6
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10 Bus Timing...............................................................................................................................205
5.11 SRAM Connection Examples.................................................................................................211
6.1
6.2
6.3
6.4
4.3.7
4.3.8
4.3.9
4.3.10
4.3.11
Block Diagrams.......................................................................................................................139
Port Register Settings When Alternate Function Is Used ..................................................170
Cautions...................................................................................................................................178
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
Features ...................................................................................................................................183
Bus Control Pins.....................................................................................................................184
5.2.1
5.2.2
Memory Block Function .........................................................................................................186
External Bus Interface Mode Control Function ...................................................................187
Bus Access..............................................................................................................................188
5.5.1
5.5.2
5.5.3
Wait Function ..........................................................................................................................197
5.6.1
5.6.2
5.6.3
5.6.4
Idle State Insertion Function..................................................................................................201
Bus Hold Function ..................................................................................................................202
5.8.1
5.8.2
5.8.3
Bus Priority..............................................................................................................................204
Overview ..................................................................................................................................213
Configuration ..........................................................................................................................214
Registers..................................................................................................................................216
Operations ...............................................................................................................................222
6.4.1
6.4.2
6.4.3
Port 9......................................................................................................................................... 122
Port CM ..................................................................................................................................... 130
Port CT...................................................................................................................................... 132
Port DH ..................................................................................................................................... 134
Port DL ...................................................................................................................................... 136
Cautions on setting port pins ..................................................................................................... 178
Cautions on bit manipulation instruction for port n register (Pn) ................................................ 181
Cautions on on-chip debug pins ................................................................................................ 182
Cautions on P05/INTP2/DRST pin ............................................................................................ 182
Cautions on P10, P11, and P53 pins when power is turned on................................................. 182
Hysteresis characteristics.......................................................................................................... 182
Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed ................ 185
Pin status in each operation mode ............................................................................................ 185
Number of clock cycles required for access .............................................................................. 188
Bus size setting function............................................................................................................ 189
Access according to bus size .................................................................................................... 190
Programmable wait function ...................................................................................................... 197
External wait function ................................................................................................................ 198
Relationship between programmable wait and external wait ..................................................... 199
Programmable address wait function ........................................................................................ 200
Functional outline ...................................................................................................................... 202
Bus hold procedure ................................................................................................................... 203
Operation in power save mode.................................................................................................. 203
Operation of each clock............................................................................................................. 222
Clock output function................................................................................................................. 223
External clock signal input ......................................................................................................... 223
User’s Manual U18953EJ5V0UD
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