UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 856

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
854
Item
LVI
Subclock oscillator
Internal oscillator
PLL
CPU
DMA
Interrupt controller
Timer P (TMP0 to TMP5)
Timer Q (TMQ0)
Timer M (TMM0)
Watch timer(/RTC)
Watchdog timer 2
Serial interface
A/D converter
D/A converter
Real-time output function (RTO)
Key interrupt function (KR)
CRC operation circuit
External bus interface
Port function
CPU register set
Internal RAM
Cautions 1. Following the store instruction to the PSC register for setting the sub-IDLE mode/low-voltage
Notes 1. Be sure to stop the PLL (PLLCTL.PLLON bit = 0) before stopping the main clock.
Be sure to observe the above sequence.
For the setting of the subclock operation mode, see 23.7.1 Setting and operation status.
3. To realize low power consumption, stop the A/D and D/A converters before shifting to the sub-IDLE
2.
2. If the sub-IDLE mode/low-voltage sub-IDLE mode is set while an unmasked interrupt request
μ
mode.
Setting of Sub-IDLE Mode
PD70F3792, 70F3793 only
sub-IDLE mode, insert the five or more NOP instructions.
signal is being held pending, the CPU does not shift to the sub-IDLE mode/low-voltage sub-
IDLE mode but executes the next instruction.
Note2
CSIB0 to CSIB4
I
UARTA0 to UARTA5
UARTC0
2
C00 to I
2
Note2
C02
Table 23-13. Operating Status in Sub-IDLE Mode
Operable
Oscillates
Oscillation enabled
Operable
Stops operation
Stops operation
Stops operation (but standby mode release is possible)
Stops operation
Stops operation
Operable when f
Operable
Operable when f
Operable when the SCKBn input clock is selected as the count clock (n = 0 to 4)
Stops operation
Stops operation (but UARTA0 is operable when the ASCKA0 input clock is selected)
Stops operation
Holds operation (conversion result held)
Holds operation (output held
Stops operation (output held)
Operable
Stops operation
See 2.2 Pin States (same operation status as IDLE1 and IDLE2 modes).
Retains status before sub-IDLE mode was set
Retains status before sub-IDLE mode was set
CHAPTER 23 STANDBY FUNCTION
When Main Clock Is Oscillating
User’s Manual U18953EJ5V0UD
R
R
/8 or f
/8 or f
XT
XT
is selected as the count clock
is selected as the count clock
Note 3
)
Operating Status
Note 3
Stops operation
Operable when f
count clock
When Main Clock Is Stopped
Note 1
XT
is selected as the