UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 796

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.3.2 Restoration
address of the restored PC.
794
Execution is returned from maskable interrupt servicing by using the RETI instruction.
When the RETI instruction is executed, the CPU performs the following processing and transfers control to the
<1> Loads the saved PC and PSW from EIPC and EIPSW, respectively, because the PSW.EP bit is 0 and the
<2> Transfers control back to the address of the restored PC and PSW.
The processing of the RETI instruction is shown below.
Note For details about the ISPR register, see 21.3.6 In-service priority register (ISPR).
Caution When the EP and NP bits are changed by the LDSR instruction during maskable interrupt
Remark
PC
PSW
PSW.NP bit is 0.
servicing, to restore the PC and PSW correctly when returning by using the RETI instruction,
the EP bit and the NP bit must be cleared to 0 using the LDSR instruction immediately before
the RETI instruction.
The solid line shows the CPU processing flow.
CHAPTER 21 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION
FEPC
FEPSW
Figure 21-6. RETI Instruction Processing
1
PC
PSW
Corresponding bit of ISPR
Return to original processing
User’s Manual U18953EJ5V0UD
RETI instruction
PSW.EP
PSW.NP
0
0
Note
EIPC
EIPSW
0
1
PC
PSW
FEPC
FEPSW