UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 321

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UPD70F3738GF-GAS-AX

Manufacturer Part Number
UPD70F3738GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3738GF-GAS-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3738GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Figure 7-64. Example of Using Software Processing to Resolve Problem When Capture Trigger Interval Is
(e) Clearing the overflow flag (TPnOVF)
Note The overflow counter is set on the internal RAM by software.
<1> The TPnCCR0 register is read (the default value of the TIPn0 pin input is set).
<2> An overflow occurs. The overflow counter is incremented and the TPnOVF bit is cleared to 0 in the
<3> An overflow occurs a second time. The overflow counter is incremented and the TPnOVF bit is
<4> The TPnCCR0 register is read.
Remark
The overflow flag (TPnOVF) can be cleared to 0 by reading the TPnOVF bit and, if its value is 1, either
clearing the bit to 0 by using the CLR1 instruction or by writing 8-bit data (with bit 0 as 0) to the TPnOPT0
register.
TPnCCR0 register
INTTPnOV signal
overflow interrupt servicing.
cleared to 0 in the overflow interrupt servicing.
The overflow counter is read.
The overflow counter is cleared to 0H.
→ If the overflow counter is N, the pulse width can be calculated by (N × 10000H + D
TIPn0 pin input
16-bit counter
In this example, because an overflow occurred twice, the pulse width is calculated as (20000H
+ D
TPnOVF bit
n = 0 to 5
counter
TPnCE bit
Overflow
a1
FFFFH
0000H
− D
Note
a0
).
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
Long (When Using TIPn0)
User’s Manual U18953EJ5V0UD
0H
D
m0
<1> <2>
1 cycle of 16-bit counter
Pulse width
D
1H
m0
<3> <4>
D
m1
2H 0H
D
m1
a1
− D
a0
).
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