UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 746

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UPD70F3738GF-GAS-AX

Manufacturer Part Number
UPD70F3738GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3738GF-GAS-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3738GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
19.16.2 Master operation in multimaster system
744
Remark
Note Confirm that the bus release status (IICCLn.CLDn bit = 1, IICCLn.DADn bit = 1) has been maintained
1
No
for a certain period (1 frame, for example). When the SDA0n pin is constantly low level, determine
whether to release the I
the product involved in the communication.
ACKEn = WTIMn = SPIEn = 1
n = 0 to 2, m = 0, 1
Set STCENn, IICRSVn
Confirm bus status
reservation enable
INTIICn interrupt
Master operation
OCKSm ← XXH
Communication
IICCLn ← XXH
IICXn ← 0XH
SVAn ← XXH
IICCn ← XXH
IICRSVn = 0?
IICFn ← 0XH
SPDn = 1?
occurred?
SPIEn = 1
IICEn = 1
Set ports
started?
START
A
Yes
Yes
Yes
Yes
(communication start
request issued)
• Waiting for slave specification from another master
• Waiting for communication start request (depending on user program)
Confirmation of bus
status is in progress
Figure 19-19. Master Operation in Multimaster System (1/3)
Note
reservation disable
Communication
(no communication start request)
Bus release status for a certain period
No
No
No
Refer to Table 4-15 Settings When Pins Are Used for Alternate Functions
to set the I
Transfer clock selection
Local address setting
Start condition setting
Slave operation
2
C0n bus (SCL0n, SDA0n pins = high level) by referring to the specifications of
B
2
C mode before this function is used.
User’s Manual U18953EJ5V0UD
STCENn = 1?
CHAPTER 19 I
INTIICn interrupt
Yes
Slave operation
SPIEn = 0
occurred?
Yes
No
2
C BUS
Waiting for communication request
No
INTIICn interrupt
SPDn = 1?
SPTn = 1
occurred?
Yes
Yes
No
No
Communication start preparation
(stop condition generation)
Waiting for stop condition
detection
Slave operation

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