UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 415
UPD70F3738GF-GAS-AX
Manufacturer Part Number
UPD70F3738GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3737GF-GAS-AX.pdf
(1071 pages)
Specifications of UPD70F3738GF-GAS-AX
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3738GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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• Compare operation
When the TQ0CE bit is set to 1, TMQ0 starts incrementing, and the output signals of the TOQ00 to TOQ03 pins
are inverted. When the value of the 16-bit counter later matches the set value of the TQ0CCRm register, a
compare match interrupt request signal (INTTQ0CCm) is generated, and the output signal of the TOQ0m pin is
inverted.
The 16-bit counter continues incrementing in synchronization with the count clock. Once the counter reaches
FFFFH, it generates an overflow interrupt request signal (INTTQ0OV) at the next clock, is cleared to 0000H, and
continues incrementing. At this time, the overflow flag (the TQ0OPT0.TQ0OVF bit) is also set to 1. The overflow
flag must be cleared to 0 by executing a CLR1 software instruction.
The TQ0CCRm register can be rewritten while the counter is incrementing. If it is rewritten, the new value is
immediately applied, and compared with the count value.
Remark
Figure 8-53. Basic Timing of Operations in Free-Running Timer Mode (Compare Function)
INTTQ0CC0 signal
INTTQ0CC1 signal
INTTQ0CC2 signal
INTTQ0CC3 signal
TQ0CCR0 register
TQ0CCR1 register
TQ0CCR2 register
TQ0CCR3 register
TOQ00 pin output
TOQ01 pin output
TOQ02 pin output
TOQ03 pin output
INTTQ0OV signal
m = 0 to 3
16-bit counter
TQ0OVF bit
TQ0CE bit
FFFFH
0000H
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
D
D
10
10
D
20
D
30
User’s Manual U18953EJ5V0UD
D
00
D
CLR1 instruction
20
Cleared to 0 by
D
30
D
D
00
11
D
20
D
30
D
00
CLR1 instruction
Cleared to 0 by
D
11
D
11
D
21
D
31
D
D
01
21
D
31
CLR1 instruction
Cleared to 0 by
D
01
D
11
D
21
D
31
D
01
413
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