UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 278

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

cleared from FFFFH to 0000H, starts incrementing, and outputs a PWM waveform from the TOPn1 pin. If the trigger
is generated again while the counter is incrementing, the counter is cleared to 0000H and restarts incrementing, and
the output of the TOPn0 pin is inverted. (The TOPn1 pin outputs a high level signal regardless of the status (high/low)
when a trigger occurs.)
time after its value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The
INTTPnCC1 compare match interrupt request signal is generated when the value of the 16-bit counter matches the
value of the CCR1 buffer register.
is used as the trigger.
276
(CCR1 buffer register)
(CCR0 buffer register)
When the TPnCE bit is set to 1, TMPn waits for a trigger. When the trigger is generated, the 16-bit counter is
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The INTTPnCC0 compare match interrupt request signal is generated when the 16-bit counter increments next
Either the valid edge of the external trigger input signal or setting the software trigger (TPnCTL1.TPnEST bit) to 1
Remark
External trigger input
TOPn0 pin output
INTTPnCC0 signal
INTTPnCC1 signal
TPnCCR1 register
TPnCCR0 register
Active level width = (Set value of TPnCCR1 register) × Count clock cycle
Cycle = (Set value of TPnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TPnCCR1 register)/(Set value of TPnCCR0 register + 1)
TOPn1 pin output
(TIPn0 pin input)
16-bit counter
Note The output from the TOPn0 pin can also be used as the input to the TIPn0 pin. When using the
TPnCE bit
n = 0 to 5
FFFFH
0000H
Figure 7-27. Basic Timing of Operations in External Trigger Pulse Output Mode
output from the TOPn0 pin as the input to the TIPn0 pin, use a software trigger instead of an
external trigger.
Note
trigger
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
Wait
for
Active level
width (D
Cycle (D
D
1
1
)
User’s Manual U18953EJ5V0UD
D
0
+ 1)
0
Active level
width (D
Cycle (D
D
1
1
)
D
0
+ 1)
0
D
D
0
1
D
1
Active level
width (D
Cycle (D
D
1
1
)
D
0
0
+ 1)