UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 580

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.7 Dedicated Baud Rate Generator
block, and generates a serial clock during transmission and reception using UARTAn. Regarding the serial clock, a
dedicated baud rate generator output can be selected for each channel.
578
The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter
There is an 8-bit counter for transmission and another one for reception.
(1) Baud rate generator configuration
(a) Base clock
(b) Serial clock generation
Note Only UARTA0 is valid; setting UARTA1 to UARTA5 are prohibited.
Remarks 1. n = 0 to 5
When the UAnCTL0.UAnPWR bit is 1, the clock selected by the UAnCTL1.UAnCKS3 to
UAnCTL1.UAnCKS0 bits is supplied to the 8-bit counter. This clock is called the base clock (f
A serial clock can be generated by setting the UAnCTL1 register and the UAnCTL2 register (n = 0 to 2).
The base clock is selected by UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits.
The frequency division value for the 8-bit counter can be set using the UAnCTL2.UAnBRS7 to
UAnCTL2.UAnBRS0 bits.
The baud rate clock is generated by dividing the serial clock by two.
ASCKA0
f
XX
f
f
f
XX
XX
XX
2. f
3. f
4. f
f
f
f
/1024
XX
XX
XX
f
f
f
/128
/256
/512
XX
XX
XX
/16
/32
/64
Note
f
XX
/2
/4
/8
XX
UCLK
UCLK
:
:
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
UAnCKS3 to UAnCKS0
/k: Serial clock (k: BRGCn register value)
Main clock frequency
Base clock frequency
Figure 16-17. Configuration of Baud Rate Generator
UAnCTL1:
UAnPWR
Selector
User’s Manual U18953EJ5V0UD
f
UAnPWR, UAnTXEn bus
UCLK
UAnBRS7 to UAnBRS0
Match detector
8-bit counter
UAnCTL2:
(or UAnRXE bit)
f
UCLK
/k
1/2
Baud rate
UCLK
).