UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 505

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) ANI0 to ANI11 pins
(2) Sample & hold circuit
(3) Compare voltage generation DAC
(4) Voltage comparator
(5) Successive approximation register (SAR)
(6) 10-bit AD conversion result register n (ADA0CRn)
(7) A/D conversion result register nH (ADA0CRnH)
(8) A/D converter mode register 0 (ADA0M0)
(9) A/D converter mode register 1 (ADA0M1)
These are analog input pins for the 12 A/D converter channels and are used to input analog signals to be
converted into digital signals. Pins other than the ones selected as analog input pins by the ADA0S register
can be used as I/O port pins.
Caution Make sure that the voltages input to the ANI0 to ANI11 pins do not exceed the rated values.
The sample & hold circuit samples each of the analog input signals selected by the input circuit and sends the
sampled data to the voltage comparator. This circuit also holds the sampled analog input signal voltage during
A/D conversion.
The compare voltage generation DAC is connected between AV
compared with the value that was sampled and held by the sample & hold circuit.
The voltage comparator compares the voltage value that was sampled and held with the output voltage of the
compare voltage generation DAC.
This register compares the voltage of the sampled analog input signal with the output voltage of the compare
voltage generation DAC (compare voltage), and sequentially retains the comparison result bit by bit starting
from the most significant bit (MSB).
When the comparison result has been held down to the least significant bit (LSB) (that is, when A/D conversion
is complete), the contents of the SAR register are transferred to the ADA0CRn register.
The ADA0CRn register is a 16-bit register that stores the A/D conversion result. ADA0ARn consist of 12
registers and the A/D conversion result is stored in the 10 higher bits of the AD0CRn register corresponding to
analog input. (The lower 6 bits are fixed to 0.)
This is a 8-bit register that stores the A/D conversion result. ADA0CRnH consists of 12 registers and the A/D
conversion result is stored in the higher 8 bits of the ADA0CRnH register corresponding to the analog input
signal.
This register specifies the operation mode and controls conversion by the A/D converter.
This register specifies the time required to convert an analog input signal to a digital signal.
Remark
In particular if a voltage of AV
channel becomes undefined, and the conversion values of the other channels may also be
affected.
n = 0 to 11
CHAPTER 14 A/D CONVERTER
User’s Manual U18953EJ5V0UD
REF0
or higher is input to a channel, the conversion value of that
REF0
and AV
SS
and generates the voltage to be
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