UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 898

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UPD70F3738GF-GAS-AX

Manufacturer Part Number
UPD70F3738GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3738GF-GAS-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3738GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
<R>
<R>
896
Note
Remarks 1. The wait time after releasing the STOP mode or IDLE2 mode is set by the OSTS register. For
Cautions 1. The actual oscillation stabilization time is longer than the theoretical value because the
μ
PD70F3792, 70F3793 only.
2. f
2.
3.
details of the OSTS register, see 23.2 (3) Oscillation stabilization time select register (OSTS).
X
overhead time after power-on is taken into consideration.
stabilization time is the time shown above, plus up to 260
: Main clock oscillation frequency
Be sure to select an oscillation stabilization time (theoretical value) of 400
it is set to less than 400
cannot be guaranteed.
Be sure to set bits 7 and 6 to “0” only in the
Address: 0000007AH
OSTS2
WDT
WDT
MD1
RMO
MD1
PIN
RES
0
1
0
1
0
0
0
0
1
1
1
1
Note
Note
Note
Operation clock (f
INTWDT2/WDTRES mode selectable
Internal oscillator clock (f
WDTRES mode fixed
Can be stopped by software
Cannot be stopped by software
OSTS1
RMO
PIN
RES
0
0
1
1
0
0
1
1
Note
Option to enable/disable stopping Internal oscillator by software
OSTS0
RES
0
1
0
1
0
1
0
1
CHAPTER 29 OPTION BYTE
0
User’s Manual U18953EJ5V0UD
X
Watchdog timer 2 mode setting
/f
μ
T
s, the internal status becomes unstable and the operation
/f
Selection of oscillation stabilization time (theoretical value)
2
2
2
2
2
2
2
2
R
10
11
12
13
14
15
16
16
) selectable
/f
/f
/f
/f
/f
/f
/f
/f
R
0
X
X
X
X
X
X
X
X
) fixed
1.638 ms
3.277 ms
6.554 ms
13.11 ms
26.21 ms
26.21 ms
409.6 s
819.2 s
2.5 MHz
0
μ
μ
μ
PD70F3737 and 70F3738.
RESOSTS2 RESOSTS1 RESOSTS0
Setting prohibited
409.6 s
819.2 s
1.638 ms
3.277 ms
6.554 ms
13.11 ms
13.11 ms
5 MHz
f
X
μ
μ
μ
s.
Setting prohibited
Setting prohibited
409.6 s
819.2 s
1.638 ms
3.277 ms
6.554 ms
6.554 ms
10 MHz
The actual oscillation
μ
μ
μ
s or longer. If

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