UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 394

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

cleared from FFFFH to 0000H, starts incrementing, and outputs a one-shot pulse from the TOQ0k pin. After the one-
shot pulse is output, the 16-bit counter is set to 0000H, stops incrementing, and waits for a trigger. If a trigger is
generated again while the one-shot pulse is being output, it is ignored.
time after its value matches the value of the CCR0 buffer register. The INTTQ0CCk compare match interrupt request
signal is generated when the value of the 16-bit counter matches the value of the CCRk buffer register.
is used as the trigger.
392
TQ0CTL1
TQ0CTL0
When the TQ0CE bit is set to 1, TMQ0 waits for a trigger. When the trigger is generated, the 16-bit counter is
The output delay period and active level width of the one-shot pulse can be calculated as follows:
The INTTQ0CC0 compare match interrupt request signal is generated when the 16-bit counter increments next
Either the valid edge of the external trigger input signal or setting the software trigger (TQ0CTL1.TQ0EST bit) to 1
Remark
Output delay period = (Set value of TQ0CCRk register) × Count clock cycle
Active level width = (Set value of TQ0CCR0 register − Set value of TQ0CCRk register + 1) × Count clock cycle
(a) TMQ0 control register 0 (TQ0CTL0)
(b) TMQ0 control register 1 (TQ0CTL1)
k = 1 to 3
TQ0CE
0/1
0
Figure 8-40. Register Settings in One-Shot Pulse Output Mode (1/3)
TQ0EST
0/1
0
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
TQ0EEE
0
0
0
0
User’s Manual U18953EJ5V0UD
0
0
TQ0MD2 TQ0MD1 TQ0MD0
TQ0CKS2 TQ0CKS1 TQ0CKS0
0/1
0
0/1
1
0/1
1
0, 1, 1:
One-shot pulse output mode
Writing 1 generates a software
trigger.
These bits select
the count clock.
0: Stop counting.
1: Enable counting.