UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 788
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UPD70F3738GF-GAS-AX
Manufacturer Part Number
UPD70F3738GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3737GF-GAS-AX.pdf
(1071 pages)
Specifications of UPD70F3738GF-GAS-AX
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3738GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Maskable
Note
Remarks 1. Default Priority: The priority order that is applied when multiple maskable interrupt requests having
Type
μ
Default
Priority
PD70F3792, 70F3793 only
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
2. The execution address of the illegal instruction when an illegal opcode exception occurs is calculated
by (Restored PC − 4).
INTUA2T
INTAD
INTDMA0
INTDMA1
INTDMA2
INTDMA3
INTKR
INTWTI
(/INTRTC2)
INTWT
(/INTRTC0)
INTRTC1
INTUA3R
INTUA3T
INTUA4R
INTUA4T
INTUC0R
INTUC0T
CHAPTER 21 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION
Name
Note
Note
Note
Note
Note
Note
Note
Note
Note
UARTA2 successive transmission enable UARTA2
A/D conversion completion
DMA0 transfer completion
DMA1 transfer completion
DMA2 transfer completion
DMA3 transfer completion
Key return interrupt
Watch timer interval/
RTC interval signal
Watch timer reference time/
RTC constant cycle signal
RTC alarm match
UARTA3 reception completion/
UARTA3 reception error
UARTA3 successive transmission enable UARTA3
UARTA4 reception completion/
UARTA4 reception error
UARTA4 successive transmission enable UARTA4
UARTC0 reception completion/
UARTC0 reception error
UARTC0 successive transmission enable UARTC0
the same priority level occur simultaneously.
priority, with 0 given the highest priority.
interrupts is INTWDT2 > NMI.
Table 21-1. Interrupt Source List (3/3)
User’s Manual U18953EJ5V0UD
Trigger
A/D
DMA
DMA
DMA
DMA
KR
WT/
RTC
WT/
RTC
RTC
UARTA3
UARTA4
UARTC0
Generating
Unit
The priority order of non-maskable
0360H
0370H
0410H
0430H
Exception
0380H
0390H
03A0H
03B0H
03C0H
03D0H
03E0H
03F0H
0400H
0420H
0440H
0450H
Code
Smaller numbers have a higher
00000360H UA2TIC
00000370H ADIC
00000380H DMAIC0
00000390H DMAIC1
000003A0H DMAIC2
000003B0H DMAIC3
000003C0H KRIC
000003D0H WTIIC/
000003E0H WTIC/
000003F0H RTC1IC
00000400H UA3RIC
00000410H UA3TIC
00000420H UA4RIC
00000430H UA4TIC
00000440H UC0RIC
00000450H UC0TIC
Address
Handler
RTC2IC
RTC0IC
Interrupt Control
Register
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