UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 307

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• Compare operation
When the TPnCE bit is set to 1, TMPn starts incrementing, and the output signals of the TOPn0 and TOPn1 pins
are inverted. When the value of the 16-bit counter later matches the set value of the TPnCCRa register, a
compare match interrupt request signal (INTTPnCCa) is generated, and the output signal of the TOPna pin is
inverted.
The 16-bit counter continues incrementing in synchronization with the count clock. Once the counter reaches
FFFFH, it generates an overflow interrupt request signal (INTTPnOV) at the next clock, is cleared to 0000H, and
continues incrementing. At this time, the overflow flag (the TPnOPT0.TPnOVF bit) is also set to 1. The overflow
flag must be cleared to 0 by executing a CLR1 software instruction.
The TPnCCRa register can be rewritten while the counter is incrementing. If it is rewritten, the new value is
immediately applied, and compared with the count value.
Remark
INTTPnCC0 signal
INTTPnCC1 signal
TPnCCR0 register
TPnCCR1 register
Figure 7-53. Basic Timing of Operations in Free-Running Timer Mode (Compare Function)
TOPn0 pin output
TOPn1 pin output
INTTPnOV signal
16-bit counter
a = 0, 1
n = 0 to 5
TPnOVF bit
TPnCE bit
FFFFH
0000H
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
D
10
D
00
CLR1 instruction
D
Cleared to 0 by
10
User’s Manual U18953EJ5V0UD
D
00
D
10
D
00
CLR1 instruction
Cleared to 0 by
D
11
D
01
CLR1 instruction
Cleared to 0 by
D
11
D
D
D
01
01
11
CLR1 instruction
Cleared to 0 by
D
11
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