UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 653

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

SIBn pin capture
INTCBnR signal
CBnTSF bit
SCKBn pin
SIBn pin
(1) Write 07H to the CBnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write A1H to the CBnCTL0 register, and select the reception mode and MSB first at the same time as
(4) The CBnSTR.CBnTSF bit is set to 1 by performing a dummy read of the CBnRX register, and the
(5) When the serial clock is input, capture the receive data of the SIBn pin in synchronization with the
(6) When reception of the data of transfer data length set by the CBnCTL2 register is completed, stop the
(7) To continue reception, read the CBnRX register with the CBnCTL0.CBnSCE bit set to 1 after the
(8) To end reception, clear the CBnSCE bit to 0.
(9) Read the CBnRX register.
(10) Clear the CBnCTL0.CBnPWR and CBnCTL0.CBnRXE bits to 0.
Remark
timing
external clock (SCKBn), and slave mode.
enabling the operation of the communication clock (f
device waits for serial clock input.
serial clock.
serial clock input and data capturing, generate the reception complete interrupt request signal
(INTCBnR) at the last edge of the serial clock, and clear the CBnTSF bit to 0.
INTCBnR signal is generated, and wait for serial clock input.
Figure 18-14. Single Transfer Mode Operation Timing (Slave Mode, Reception Mode)
(1)
(2)
(3)
n = 0 to 4
(4)
(5)
Bit 7
Bit 6
CHAPTER 18 CLOCKED SERIAL INTERFACE B (CSIB)
Bit 5 Bit 4
Bit 3 Bit 2
User’s Manual U18953EJ5V0UD
Bit 1
(6)
Bit 0
(7)
CCLK
Bit 7
).
Bit 6
Bit 5 Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
(8)
(9)
(10)
CCLK
) =
651