UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 349

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) Basic counter operation
The basic operation of the 16-bit counter is described below. For more details, see the descriptions of each
operating mode.
(a) Starting counting
(b) Clearing TMQ0
(c) Overflow
(d) Reading TMQ0 while it is incrementing
TMQ0 starts counting from FFFFH in all operating modes, and increments as follows: FFFFH, 0000H,
0001H, 0002H, 0003H….
TMQ0 is cleared to 0000H when its value matches the value of the compare register or when the value of
TMQ0 is captured upon the input of a valid capture trigger signal.
Note that when TMQ0 increments from FFFFH to 0000H after it starts counting and immediately following
an overflow, it does not mean that TMQ0 has been cleared. Consequently, the INTTQ0CCm interrupt is
not generated in this case (m = 0 to 3).
TMQ0 overflows after it increments from FFFFH to 0000H in free-running timer mode and pulse width
measurement mode. An overflow sets the TQ0OPT0.TQ0OVF bit to 1 and generates an interrupt request
signal (INTTQ0OV). Note that INTTQ0OV will not be generated in the following cases:
• When TMQ0 has just started counting.
• When the compare value at which TMQ0 is cleared is specified as FFFFH.
• In pulse width measurement mode, when TMQ0 increments from FFFFH to 0000H after being cleared
Caution After the INTTQ0OV overflow interrupt request signal occurs, be sure to confirm that
TMQ0 can be read while it is incrementing by using the TQ0CNT register.
Specifically, the value of TMQ0 can be read by reading the TQ0CNT register while the TQ0CLT0.TQ0CE
bit is 1. Note, however, that when the TQ0CLT0.TQ0CE bit is 0, the value of TMQ0 is always FFFFH and
the value of the TQ0CNT register is always 0000H.
when its value of FFFFH was captured.
the overflow flag (TQ0OVF) is set to 1.
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
User’s Manual U18953EJ5V0UD
347