UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 416

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

414
• Capture operation
When the TQ0CE bit is set to 1, the 16-bit counter starts incrementing. When it is detected that a valid edge as
been input to the TIQ0m pin, the value of the 16-bit counter is stored in the TQ0CCRm register, and a capture
interrupt request signal (INTTQ0CCm) is generated.
The 16-bit counter continues incrementing in synchronization with the count clock. When the counter reaches
FFFFH, it generates an overflow interrupt request signal (INTTQ0OV) at the next clock, is cleared to 0000H, and
continues incrementing. At this time, the overflow flag (the TQ0OPT0.TQ0OVF bit) is also set to 1. The overflow
flag must be cleared to 0 by executing a CLR1 software instruction.
Remark
Remark
Figure 8-54. Basic Timing of Operations in Free-Running Timer Mode (Capture Function)
INTTQ0CC0 signal
INTTQ0CC1 signal
INTTQ0CC2 signal
INTTQ0CC3 signal
TQ0CCR0 register
TQ0CCR1 register
TQ0CCR2 register
TQ0CCR3 register
INTTQ0OV signal
m = 0 to 3
The valid edge is the rising edge.
TIQ00 pin input
TIQ01 pin input
TIQ02 pin input
TIQ03 pin input
16-bit counter
TQ0OVF bit
TQ0CE bit
FFFFH
0000H
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
0000
0000
0000
0000
D
20
D
00
D
30
D
User’s Manual U18953EJ5V0UD
10
CLR1 instruction
D
Cleared to 0 by
00
D
D
20
D
01
D
10
30
D
11
D
21
D
31
D
CLR1 instruction
01
Cleared to 0 by
D
11
D
12
D
D
D
21
02
31
D
22
D
32
D
D
CLR1 instruction
Cleared to 0 by
02
12
D
03
D
D
D
13
32
22
D
D
33
03
D
23
D
13
D
D
33
23