UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 627

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.8 Cautions
(1) When the clock supply to UARTC0 is stopped (for example, in IDLE1, IDLE2, or STOP mode), the operation
(2) In UARTC0, the interrupt caused by a communication error does not occur. When transferring transmit data
(3) Start up UARTC0 in the following sequence.
(4) Stop UARTC0 in the following sequence.
(5) In transmit mode (UC0CTL0.UC0PWR bit = 1 and UC0CTL0.UC0TXE bit = 1), do not overwrite the same
(6) In continuous transmission, the period from the stop bit to the next start bit is 2 base clock cycles longer than
(7) UARTC cannot identify the start bit if low level signals are continuously input to the RXDC0 pin.
(8) The RXDC0 and SIB1 pins cannot be used at the same time. When using the pin for RXDC0, stop CSIB0
and receive data using DMA transfer, error processing cannot be performed even if errors (parity, overrun,
framing) occur during transfer. Either read the UC0STR register after DMA transfer has been completed to
make sure that there are no errors, or read the UC0STR register during communication to check for errors.
<1> Set the UC0CTL0.UC0PWR bit to 1.
<2> Set the ports.
<3> Set the UC0CTL0.UC0TXE bit to 1 and the UC0CTL0.UC0RXE bit to 1.
value to the UC0TX register by software because transmission starts by writing to this register. To transmit the
same value continuously, overwrite the same value.
usual. However, the reception side initializes the timing by detecting the start bit, so the reception result is not
affected.
reception. (clear the CB1CTL0.CB1RXE bit to 0.) When using the pin for SIB1 , stop UARTC0 reception. (clear
the UC0CTL0.UC0RXE bit to 0.)
stops with each register retaining the value it had immediately before the clock supply was stopped. The
TXDC0 pin output also holds and outputs the value it had immediately before the clock supply was stopped.
However, the operation is not guaranteed after the clock supply is resumed. Therefore, after the clock supply
is resumed, the circuits should be initialized by setting the UC0CTL0.UC0PWR, UC0CTL0.UC0RXEn, and
UC0CTL0.UC0TXEn bits to 0, 0, 0.
<1> Set the UC0CTL0.UC0TXE bit to 0 and the UC0CTL0.UC0RXE bit to 0.
<2> Set the ports and set the UC0CTL0.UC0PWR bit to 0 (it is not a problem if the port settings are not
changed).
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (
User’s Manual U18953EJ5V0UD
PD70F3792, 70F3793)
625